The invention relates generally to integrated circuits and, in particular, to methods and assemblies for extending the useful lifetime of an integrated circuit.
The operating requirements of an integrated circuit apply stress on the constituent devices, which may reduce performance over time and cause reliability problems. In particular, complementary metal oxide semiconductor (CMOS) field-effect transistors may experience shifts in electrical parameters and adverse changes in performance over their useful lifetime when biased and operated in an end product.
One effect that may reduce the useful lifetime of CMOS field-effect transistors is interface degradation during operation. Interface degradation may originate from an increase in trap density at device interfaces, such as interfaces with the gate dielectric layer, caused by voltage stress over time. Because of the trapping of charge carriers, the switching characteristics of the CMOS field-effect transistor can be changed. Another effect that may reduce the useful lifetime of CMOS field-effect transistors is the presence of mobile carriers in the gate dielectric layer. These mobile carriers trigger numerous physical damage processes that can drastically change the device electrical parameters over prolonged periods of operation. For example, damage accumulation can eventually cause the integrated circuit to fail by causing shifts in the threshold voltages of the CMOS field-effect transistors.
Improved methods and structures are needed to counteract or reverse shifts in electrical parameters and performance degradation experienced by CMOS field-effect transistors over their useful lifetime.